Arduino and dev kits get you to a demo. Custom PCBs get you to form factor, unit cost, power budget, and certifications, whether that is a soil sensor for agritech or a wearable companion to a cloud AI product.
At PAI Technologies we run software and hardware in one Delhi studio so firmware, API, and board constraints are designed together. Our TerraSenti engagement for MythraCore Ltd (UK) is a live example: custom soil-sensing PCB from schematic through JLCPCB prototypes and bring-up documentation.
This guide walks through how we move from KiCad schematic to manufacturing-ready outputs without the rework that burns calendar time and prototype budgets.
When off-the-shelf boards stop working
Off-the-shelf modules hide BOM cost at scale, impose awkward enclosures, and couple you to pinouts you did not choose. Custom design pays off when sampling rate, sensor fusion, radio choice, or power envelope are product differentiators.
MythraCore’s TerraSenti path started with field constraints: soil chemistry interfaces, weather exposure, and what the cloud backend must ingest, not “we need a PCB” in isolation.
If software and hardware are split across vendors, pin counts and ADC choices get negotiated late. One studio means the API contract and the analog front-end are agreed in the same standup.
Schematic first: blocks, power, and test points
We capture hierarchy in KiCad with clear sheet boundaries: power, MCU/radio, sensors, connectors. Every rail gets decoupling sized for the load. Programming headers and test points are placed before layout, not as an afterthought on rev B.
Run ERC on every commit; treat warnings as errors for production designs. Document alternate parts (MPN + LCSC/JLCPCB C-number) in the BOM so assembly does not stop on one shortage.
Keep analog and digital returns separated where noise matters, soil and environmental sensing often do. Simulation and bench validation on the schematic sheet reduce surprises at first power-on.
- Block diagram agreed with firmware and cloud owners
- Power budget table (active, sleep, peak transmit)
- Connector and enclosure keep-out notes from mechanical review
Layout, impedance, and DRC discipline
Stack-up and controlled impedance follow your fab’s capabilities. We align with JLCPCB four-layer defaults unless RF sections need custom stack-ups, then we confirm with the fab before routing critical nets.
Courtyard checks, teardrops, and thermal relief on planes are part of DRC, not cosmetic. High-current paths and battery management get explicit copper width and via stitching.
Design for test: accessible ground clips, labelled test points, and UART/SWD reachable without disassembling the enclosure when possible.
BOM optimisation for JLCPCB assembly
Every line item maps to an LCSC C-number where possible. We flag parts that are frequently out of stock and pre-approve alternates with the same footprint.
Consolidate passives to standard values when tolerance allows: fewer reel changes, lower assembly friction. DNP (do not populate) lines are explicit for rev-specific builds.
Export BOM CSV, pick-and-place, and assembly notes in the format JLCPCB expects. Photos or diagrams for polarised parts reduce wrong-orientation rejects on first assembly lot.
Gerbers, prototypes, and bring-up
Before Gerber export: final DRC, drill file review, and board outline matching enclosure CAD. Order five to ten prototypes before scaling to 100+ unless risk is very low.
Bring-up plan: current-limited bench supply, current profile check, UART/SWD first, then sensor validation scripts tied to what the cloud expects (sampling rate, units, calibration).
Hand over KiCad project, Gerbers, BOM, pick-and-place, and a one-page bring-up guide. MythraCore-style clients can run field trials without waiting on our bench for every unit.
Software handoff alongside the board
Firmware images, OTA strategy, and device provisioning docs ship with the hardware package. If Gordon-class cloud features consume sensor data, the ingestion schema is versioned with the PCB rev.
Not every engagement needs custom PCB: when dev kits suffice, we stay software-only. When form factor and unit economics force custom design, KiCad-to-JLCPCB is a single roadmap inside PAI.
Send enclosure constraints, target BOM, and field environment in your brief; we will estimate schematic-through-prototype time in one reply.